HDL Coder

Verifying HDL Code

HDL Coder generates VHDL and Verilog test benches for rapid verification of generated HDL code. You can customize an HDL test bench using a variety of options that apply stimuli to the HDL code. You can also generate script files to automate the process of compiling and simulating your code in HDL simulators.

HDL Coder works with HDL Verifier to automatically generate two types of cosimulation models:

  • HDL cosimulation model, for performing HDL cosimulation with Simulink and an HDL simulator, such as Cadence Incisive or Mentor Graphics ModelSim and Questa
  • FPGA-in-the-loop (FIL) cosimulation model, for verifying your design with Simulink and an FPGA board
Automatically generated FGPA-in-the-loop (FIL) model for video sharpening.
Automatically generated FPGA-in-the-loop (FIL) model for video sharpening. FIL simulation lets you efficiently perform design space exploration on your hardware.
Next: Documenting and Tracing HDL Code

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VHDL y Verilog para FPGA con MATLAB y Simulink

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