HDL Coder

Generating HDL Code

HDL Coder lets you generate synthesizable HDL code for FPGA and ASIC implementations in a few steps:

  • Model your design using a combination of MATLAB code, Simulink blocks, and Stateflow charts.
  • Optimize models to meet area-speed design objectives.
  • Generate HDL code using the integrated HDL Workflow Advisor for MATLAB and Simulink.
  • Verify generated code using HDL Verifier.

HDL Code Generation from MATLAB

The HDL Workflow Advisor in HDL Coder automatically converts MATLAB code from floating-point to fixed-point and generates synthesizable VHDL and Verilog code. This capability lets you model your algorithm at a high level using abstract MATLAB constructs and System objects while providing options for generating HDL code that is optimized for hardware implementation. HDL Coder provides a library of ready-to-use logic elements, such as counters and timers, which are written in MATLAB.

HDL Code Generation from Simulink

The HDL Workflow Advisor generates VHDL and Verilog code from Simulink and Stateflow. With Simulink, you can model your algorithm using a library of more than 200 blocks, including Stateflow charts. This library provides complex functions, such as the Viterbi decoder, FFT, CIC filters, and FIR filters, for modeling signal processing and communications systems and generating HDL code.

HDL Coder Workflow Advisor for Simulink.
HDL Coder Workflow Advisor for Simulink. You can generate HDL code to program Xilinx and Altera FPGAs by connecting directly to Xilinx ISE and Altera Quartus II.
Next: Optimizing HDL Code

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